Sibbi's z80 reference page

Addressing	Meaning
Immediate	In Immediate addressing the byte following the op code in memory contains the operand. An example of this is to load the Accumulator with a constant, byte follows immediately after the opcode.
Immediate Extended	In Immediate extended addressing, the two bytes following the op code in memory, contain the operand. An example of this is to load the HL register pair with a 16-bit memory address.
Modified Zero Page	This is used in the modified CALL instruction RST, to set the Program Counter (PC) to an address in zero-page memory. The value this brings is that a single 8-bit instruction can be used to call commonly used subroutines, saving memory.
Relative	This uses one byte following the op code as a displacement to jump to. This signed two's complement number can range +127 to -128 from A+2, giving an effective range of +129 to -126 to jump to, relative from the current code address, allowing reduced memory use and relocatable code.
Extended	In extended addressing two bytes follow the op code, to indicate a jump point or an address at which a value can be located. It is required to jump somewhere in memory, or to load and store data from memory. The notation nn is used to represent the address, in low byte, high byte order. The value is in parentheses indicating that nn is a reference to a value in memory at (nn)
Indexed	In the indexed addressing mode the byte of data following the op code contains a displacement. The displacement, a two's complement signed number, d, will be added to the index register. The contents of the index registers are not modified in these instructions. An example is to load the accumulator with a value pointed at by the Index Register plus the two's complement displacement. Two registers are included because operations may require two or more tables, and their base addresses can then be stored separately. The two index registers are represented as IX and IY and the displacement by d, and together they are referenced as (IX+d) and (IY+d).
Register	In Register addressing the value from one register is read into another register
Implied	Implied addressing refers to addressing where the opcode implies one or more cpu registers as containing the operands to use. This for example is the case in arithmetic operations like SUB where the destination is implied to be the accumulator.
Register indirect	Implies a 16-bit register pair (such as HL) being used as a pointer to a memory location. An example is to load the accumulator with a value pointed to by the HL register pair (HL). Indexed addressing is Register indirect addressing, with a displacement.
Bit	Bit addressing is used in instructions where the last three bits of the opcode select a particular bit, of a register or memory value to modify. The register or memory value to change have already been selected with any of the addressing modes referenced above.
Combinations	Many instructions include more than one operand, such as a src and dst operand, where different modes can be used for each. One example is the LD instruction which can use immediate to specify the source and Register indirect or Indexed to specify the destination

	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→	←Tcycle→
Clock	High	Low	High	Low	High	Low	High	Low	High	Low	High	Low	High	Low	High	Low	High	Low	High	Low
Mcycle	← Machine Cycle →	← Machine Cycle →	← Machine Cycle →
Number	← M1 →	← M2 →	← M3 →
Mname	← Opcode Fetch →	← Memory Read →	← Memory Write →
Icycle	← Instruction Cycle →
Speed	Above example shows a hypothetical instruction taking 10-Cycles to execute As shown in this example, memory access is expensive, making use of the many registers is therefore vital to perfomance Machine Cycles (MC) in this example are 3, Time Cycles or Time States (TS) are 10 At 4Mhz = 4.000.000 T-cycles/second we can Estimate time (ET) as 1/(4.000.000/10) Seconds or 10 μsec 4.000.000 / 10 t-cycles for this instruction means we can execute this instruction 400.000 times per second Timing for instructions is given in MC (Machine Cycles), TS (Time States/Cycles) and ET (Estimated time in Microseconds)

Flags	S	Z	X	H	X	P/V	N	C
Bit	7	6	5	4	3	2	1	0
Name	Sign	Zero	Not used	Half Carry	Not used	Parity / Overflow	Add / Subtract	Carry
cc when 1	Sign Negative (M)	Zero (Z)	Not used	Not used	Not used	Parity Even (PE)	Not used	Carry (C)
cc when 0	Sign Positive (P)	Non-Zero (NZ)	Not used	Not used	Not used	Parity Odd (PO)	Not used	No Carry (NC)

Flag	Use
C	Used as a carry or borrow flag for add and sub. DAA uses the carry flag if appropriate. The shift commands RLA, RAA, RLS and RSS use the carry bit as a link between the LSB and MSB. The RLCA, RLC and SLA instructions use the carry flag for the final value shifted out of bit 7 of a register or memory location. The RRCA, RRC and SRL instructions use the carry bit to contain the value of bit 0 of a register or memory location. The logic instructions AND, OR and XOR reset the carry flag. The flag instruction SCF sets the carry flag and its sister CCF resets it.
N	The add/subtract flag is used by the DAA instruction to distinguish between the add and sub instructions. For add N is cleared, for sub, N is set as 1
P/V	The parity/overflow (P/V) flag is set to a specific state depending on the operating being performed. For arithmetic operations, the flag indicates overflow when the number is greater than the maximum possible (+127) or less than the minimum (-128), using the sign bit to detect overflow. It is also set when adding two positive numbers result in a negative outcome, or if subtracting two negative numbers results in a positive outcome. With logic and rotate instructions the flag indicates odd parity (P=0) for an odd number or even parity (P=1) for an even number. During CPI, CPIR, CPD and CPDR as well as LDI, LDIR, LDR and LDDR the P/V flag monitors the state of the Byte Counter (register B). If the byte counter decrements to 0 the flag is cleared (P=0), otherwise it is set (P=1). During LD A, I and A, R, the P/V flag stores the interrupt enable bit of IFF2. When inputting bytes with the IN r, (C) instruction the P/V flag contains the parity of the data.
H	The Half Carry (H) flag is set (H=1) or cleared (H=0) depending on the Carry and Borrow status between bits 3 and 4 of an 8-bit arithmetic operation. The flag is used by the DAA instruction to correct the result of a packed BCD add or subtract operation. The H flag is set (H=1) when a carry occurs from bit 3 to bit 4, otherwise reset (H=0). The H flag is set (H=1) when a borrow from bit 4 occurs, otherwise reset (H=0).
Z	The Zero Flag (Z) is set (Z=1) or cleared (Z=0) if the result generated by the execution of a instruction is 0. For 8-bit arithmetic and logical operations, the Z flag is set to 1 if the result byte in the Accumulator is 0. If not, the flag is reset (Z=0). For compare instructions the Z flag is set to 1 if the value in the Accumulator is equal to the value in memory location indicated by the value in register pair HL. When testing a bit in a register or memory location, the Z flag contains the complemented (negated) state of the indicated bit. When inputting or outputting a byte between a memory location and an INI, IND, OUTI or OUTD I/O device, if the result of decrementing register B (the byte counter) is 0, the Z flag is set to 1, otherwise the Z flag is 0. For bytes input from I/O device using the IN r, (C) the Z flag is set to indicate a 0-byte input.
S	The Sign Flag (S) stores the state of the most significant bit (bit 7) of the Accumulator. When the z80 performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information. A positive number is indicated by a S=0, a negative number is indicated by a S=1. The binary equivalent of a positive number is stored in bits 0 to 6 for a range from 0 to 127. A negative number is represented by the twos-complement of the equivalent positive number the total range for negative numbers is -1 to -128. When inputting a byte of data from an I/O device using the IN r, (C) the S flag indicates either a positive (S=0) or negative (S=1) data.

Notation	Meaning
(HL)	Identifies the contents of a memory location, pointed to by the contents of memory registers H and L. Low order byte is in H and high order in L
(IX+d) / (IY+d)	Identifies the contents of a memory location which is the combination of the address in IX/IY plus the signed displacement d (-128 to +127)
b	A one bit expression in the range 0 to 7, identifying the number of a bit, in a byte
cc	The status of a Flag Register as any of the (NZ, Z, NC, C, PO, PE, P or M) for conditional jumps, calls and return instructions
d	A one byte signed integer in the range -128 to +127
dd	Identifies any of the register pairs (BC, DE, HL, or SP)
e	A one byte signed integer expression in the range -126 to +129 for a relative jump offset from the current location
m	Identifies any of the r, (HL), (IX+d) or (IY+d)
n	A one byte integer in the range 0-255
nn	A two byte integer in the range 0-65535, first byte being the low order byte
qq	Identifies any of the register pairs (BC, DE, HL or AF)
pp	Identifies any of the register pairs (BC, DE, IX or SP)
r	Any of the registers A, B, C, D, E, H or L
rr	Identifies any of the register pairs (BC, DE, IX or SP)
ss	Identifies any of the register pairs (BC, DE, HL or SP)

ADC - ADd with Carry

Add register or memory contents, with or without an offset to the accumulator with carry.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

ADC A, r

Source→ Dest↓	A	B	C	D	E	H	L
ADC	$8F	$88	$89	$8A	$8B	$8C	$8D

A

r = (a, b, c, d, e, h, l)

A ← A + r + CY

A, r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

Contents of register r along with the Carry Flag (Register F) are added to the Accumulator and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Immediate-to-Implied

ADC A, n

Source→ Dest↓	n
ADC	$CEn

A

n

A ← A + n

A, n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Contents of integer n along with the Carry Flag (Register F) are added to the Accumulator and the result is stored in the Accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Register-Indirect-to-Implied

ADC A, (HL)

Source→ Dest↓	(HL)
ADC	$8E

A

(HL)

A ← A + (HL)

A, (HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

The byte at the address pointed to by the HL register pair along with the Carry Flag (Register F) is added to the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Indexed-to-Implied

ADC A, (IX+d)

Source→ Dest↓	(IX+d)
ADC	$DD8Ed

A

(IX+d)

A ← A + (IX+d)

A, (IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IX register to the two's complement displacement d along with the Carry Flag (Register F), is added to the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Indexed-to-Implied

ADC A, (IY+d)

Source→ Dest↓	(IY+d)d
ADC	$FD8E

A

(IY+d)

A ← A + (IY+d)

A, (IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IY register to the two's complement displacement d along with the Carry Flag (Register F), is added to the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register

ADC HL, ss

Source→ Dest↓	BC	DE	HL	SP
ADC HL	$ED4A	$ED5A	$ED6A	$ED7A

HL

ss =( bc, de, hl, sp)

HL ← HL + ss + CY

HL, ss

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

4 / 15 / 3.75

The contents of register pairs bc, de, hl or sp are added to the contents of register pair hl along with carry flag (C flag in F register) and the result is stored in HL
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 11, otherwise it is reset.
P/V is set if overflow, otherwise it is reset.
N is reset, C is set if carry from bit 15, otherwise reset

ADD - ADD number

Add register or memory contents, with or without an offset, to the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register

ADD A, r

Source→ Dest↓	A	B	C	D	E	H	L
ADD	$87	$80	$81	$82	$83	$84	$85

A

r = (a, b, c, d, e, h, l)

A ← A + r

A, r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

The contents of register r are added to the accumulator and the result is stored in the accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Immediate-to-Register

ADD A, n

Source→ Dest↓	n
ADD	$C6n

A

n

A ← A + n

A, n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Integer n is added to the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Register-Indirect-to-Register

ADD A, (HL)

Source→ Dest↓	(HL)
ADD	$88

A

(HL)

A ← A + (HL)

A, (HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

The byte stored at the memory address pointed to by the HL register pair is added to the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Indexed-to-Register

ADD A, (IX+d)

Source→ Dest↓	(IX+d)
ADD	$DD86d

A

(IX+d)

A ← A + (IX+d)

A, (IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IX register to the two's complement displacement d, is added to the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

Indexed-to-Register

ADD A, (IY+d)

Source→ Dest↓	(IY+d)
ADD	$FD86d

A

(IY+d)

A ← A + (IY+d)

A, (IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IY register to the two's complement displacement d, is added to the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register

ADD HL, ss

Source→ Dest↓	BC	DE	HL	SP
ADD HL	$09	$19	$29	$39

HL

ss =( bc, de, hl, sp)

HL ← HL + ss

HL, ss

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

3 / 11 / 2.75

The contents of register pairs bc, de, hl or sp are added to the contents of register pair hl and the result is stored in HL
S, Z, P/V are not affected.
N is reset
H is set if carry from bit 11, otherwise it is reset.
C is set if carry from bit 15, otherwise reset

Register-to-Register

ADD IX, pp

Source→ Dest↓	BC	DE	IX	SP
ADD IX	$DD09	$DD19	$DD29	$DD39

IX

pp =( bc, de, ix, sp)

IX ← IX + pp

IX, pp

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

3 / 11 / 2.75

The contents of register pairs bc, de, ix or sp are added to the contents of Index register X and the result is stored in IX
S, Z, P/V are not affected.
N is reset
H is set if carry from bit 11, otherwise it is reset.
C is set if carry from bit 15, otherwise reset

Register-to-Register

ADD IY, rr

Source→ Dest↓	BC	DE	IY	SP
ADD IY	$FD09	$FD19	$FD29	$FD39

IY

rr =( bc, de, iy, sp)

IY ← IY + rr

IY, rr

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

3 / 11 / 2.75

The contents of register pairs bc, de, iy or sp are added to the contents of Index register Y and the result is stored in IY
S, Z, P/V are not affected.
N is reset
H is set if carry from bit 11, otherwise it is reset.
C is set if carry from bit 15, otherwise reset

AND - Perform logical AND with accumulator

Perform a logical AND operation between a register, integer or memory address, with or without offset, to the accumulator and store the result in the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

AND r

Source→ Dest↓	A	B	C	D	E	H	L
AND	$A7	$A0	$A1	$A2	$A3	$A4	$A5

A

a, b, c, d, e, h, l

A ← A ^ r

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

A logical AND operation is performed between the contents of r and the accumulator and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Immediate-to-Implied

AND n

Source→ Dest↓	n
AND	$E6n

A

n

A ← A ^ n

n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical AND operation is performed between the integer n and the contents of the Accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Register-Indirect-to-Implied

AND (HL)

Source→ Dest↓	(HL)
AND	$A6

A

(HL)

A ← A ^ (HL)

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical AND operation is performed between the byte at the address pointed to by the HL register pair and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

AND (IX+d)

Source→ Dest↓	(IX+d)
AND	$DDA6d

A

(IX+d)

A ← A ^ (IX+d)

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical AND operation is performed between the byte at the address generated by adding the contents of the IX register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

AND (IY+d)

Source→ Dest↓	(IY+d)
AND	$FDA6d

A

(IY+d)

A ← A ^ (IY+d)

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical AND operation is performed between the byte at the address generated by adding the contents of the IY register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator to the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is set if carry from bit 7, otherwise is reset.

BIT - Test BIT

Test a bit in register or memory, with or without offset and set the Z flag accordingly.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

BIT b, r

Source→ Dest Bit↓	A	B	C	D	E	H	L
0	$C847	$C840	$C841	$C842	$C843	$C844	$C845
1	$C84F	$C848	$C849	$C84A	$C84B	$C84C	$C84D
2	$C857	$C850	$C851	$C852	$C853	$C854	$C855
3	$C85F	$C858	$C859	$C85A	$C85B	$C85C	$C85D
4	$C867	$C860	$C861	$C862	$C863	$C864	$C865
5	$C86F	$C868	$C869	$C86A	$C86B	$C86C	$C86D
6	$C877	$C870	$C871	$C872	$C873	$C874	$C875
7	$C87F	$C878	$C879	$C87A	$C87B	$C87C	$C87D

Z

r=(a,b,c,d,e,h,l)

Z ← inverse(rb)

b, r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

2 / 8 / 4.50

Tests bit b in register r and records result in Z.
Z becomes zero if bit b is 1, reset otherwise.
H is set, S and P/V are unknown, N is reset, C is not affected

Register-Indirect

BIT b, (HL)

Source→ Dest Bit↓	(HL)
0	$C846
1	$C84E
2	$C856
3	$C85E
4	$C866
5	$C86E
6	$C876
7	$C87E

Z

(HL)

Z ← inverse((HL)b)

b, (HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 12 / 3.00

Tests bit b in byte pointed to by memory location stored in register pair HL and records result in Z.
Z becomes zero if bit b is 1, reset otherwise.
H is set, S and P/V are unknown, N is reset, C is not affected

Indexed

BIT b, (IX+d)

Source→ Dest Bit↓	(IX+d)
0	$DDC8d46
1	$DDC8d4E
2	$DDC8d56
3	$DDC8d5E
4	$DDC8d66
5	$DDC8d6E
6	$DDC8d76
7	$DDC8d7E

Z

(IX+d)

Z ← inverse((IX+d)b)

b, (IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 12 / 3.00

Tests bit b in byte stored at the memory address generated by adding the contents of the IX register to the two's complement displacement d and records result in Z.
Z becomes zero if bit b is 1, reset otherwise.
H is set, S and P/V are unknown, N is reset, C is not affected

Immediate with absolute offset

BIT b, (IY+d)

Source→ Dest Bit↓	(IY+d)
0	$FDC8d46
1	$FDC8d4E
2	$FDC8d56
3	$FDC8d5E
4	$FDC8d66
5	$FDC8d6E
6	$FDC8d76
7	$FDC8d7E

Z

(IY+d)

Z ← inverse((IY+d)b)

b, (IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 12 / 3.00

Tests bit b in byte stored at the memory address generated by adding the contents of the IY register to the two's complement displacement d and records result in Z.
Z becomes zero if bit b is 1, reset otherwise.
H is set, S and P/V are unknown, N is reset, C is not affected

CALL - CALL a subroutine

Unconditionally or conditionally pushes current PC to stack. SP-1 becomes current PC high byte, and SP-2 becomes current PC low byte.
The current PC can be popped off the stack and execution continued at calling location by using the ret instruction.
No flags are affected, please never call me.

The following table shows the conditions possible and their relevant flags.

Condition	Flag
Sign-Positive (P)	S
Sign-Negative (N)	S
Non-Zero (NZ)	Z
Zero (Z)	Z
Parity-Odd (PO)	P/V
Parity-Even (PE)	P/V
No-Carry (NC)	C
Carry (C)	C

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Immediate-Extended

CALL nn

Source→ Dest↓	nn
PC=nn	$CDnn

PC

nn

(SP – 1) ← PCH
(SP – 2) ← PCL
PC ← nn

nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 17 / 4.25

Push PC to stack, call subroutine at address nn.

Immediate-Extended

CALL cc, nn

Source→ Dest↓	NZ, nn	Z, nn	NC, nn	C, nn	PO, nn	PE, nn	P, nn	M, nn
PC	$C4nn	$CCnn	$D4nn	$DCnn	$E4nn	$ECnn	$F4nn	$FCnn

PC

cc, nn

IF cc true {
(SP – 1) ← PCH
(SP – 2) ← PCL
PC ← nn }

nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

IF cc == true
5 / 17 / 4.25
IF cc == false
3 / 10 / 2.50

If cc (according to table above) is True, Push PC to stack
Call subroutine at address nn.

CCF - Complement Carry Flag

The carry flag in the F register is inverted.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

CCF

Source→ Dest↓	CY
invert(CY)	$3F

CY

None

CY ← invert(CY)

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Inverts the carry flag in the F register.
The H bit is set to previous carry.
C is set 0 if carry was set, otherwise reset

CP - ComPare

Performs a compare operation between a register, integer or memory address, with our without offset, to the contents of the accumulator and sets the Z flag accordingly.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

CP r

Source→ Dest↓	A	B	C	D	E	H	L
CP	$BF	$B8	$B9	$BA	$BB	$BC	$BD

A

a, b, c, d, e, h, l

A - r

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

Compares the contents of register r to the contents of the Accumulator and sets the Z flag if a true comparison is made.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise is reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise reset

Immediate-to-Implied

CP n

Source→ Dest↓	n
CP	$FEn

A

n

A - n

n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Compares the integer n to the contents of the Accumulator and sets the Z flag if a true comparison is made.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise is reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise reset

Register-Indirect-to-Implied

CP (HL)

Source→ Dest↓	(HL)
CP	$BE

A

(HL)

A - (HL)

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Compares the byte stored at the memory address pointed to by the combination of the HL registers to the contents of the Accumulator and sets the Z flag if a true comparison is made.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise is reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise reset

Indexed-to-Implied"

CP (IX+d)

Source→ Dest↓	(IX+d)
CP	$DDBEd

A

(IX+d)

A - (IX+d)

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

Compares the byte at the address generated by adding the contents of the IX register to the two's complement displacement d, and the accumulator and sets the Z flag if a true comparison is made.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise is reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise reset

Indexed-to-Implied

CP (IY+d)

Source→ Dest↓	(IY+d)
CP	$FDBEd

A

(IY+d)

A - (IY+d)

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

Compares the byte at the address generated by adding the contents of the IY register to the two's complement displacement d, and the accumulator and sets the Z flag if a true comparison is made.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise is reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise reset

CPD - ComPare and Decrement

The contents of the memory location addressed by the HL register is compared with the contents of the accumulator. If the compare is true, Z is set. HL is then decremented and the BC counter register pair (B and C) is decremented.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Immediate to Register

CPD

Source→ Dest↓	(HL)/th>
A	$(ED)A9

A

(HL)

A - (HL)
HL ← HL - 1
BC ← BC -1

None

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

4 / 16 / 4.0

Contents of memory location address by the HL pair is compared to the contents of the accumulator.
Z is set if true otherwise reset,
S is set if result is negative otherwise reset,
H is set if borrow from bit 4 otherwise reset,
P/V is set if BC - 1 is not 0, reset otherwise,
N is set. HL is decremented, BC is decremented

CPDR - ComPare and Decrement Repeat

The contents of the memory location addressed by the HL register is compared with the contents of the accumulator. If the compare is true, Z is set. HL is then decremented and the BC counter register pair (B and C) is decremented. This is repeated until A equals (HL) or until BC reaches 0, whichever comes first.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

CPDR

Source→ Dest↓	(HL)/th>
A	$(ED)B9

A

(HL)

A - (HL)
HL ← HL - 1
BC ← BC -1

None

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

A = (HL) or BC == 0
4 / 16 / 4.00
If A ≠ 0 and BC ≠ 0
5 / 21 / 5.25

Contents of memory location address by the HL pair is compared to the contents of the accumulator.
Z is set if true otherwise reset,
S is set if result is negative otherwise reset,
H is set if borrow from bit 4 otherwise reset,
P/V is set if BC - 1 is not 0, reset otherwise,
N is set. HL is decremented, BC is decremented. This operation is repeated until (HL) equals A or until BC reaches 0, whichever comes first.

CPI - ComPare and Increment

The contents of the memory location addressed by the HL register is compared with the contents of the accumulator. If the compare is true, Z is set. HL is then incremented and the BC counter register pair (B and C) is decremented.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

CPI

Source→ Dest↓	(HL)/th>
A	$(ED)A1

A

(HL)

A - (HL)
HL ← HL + 1
BC ← BC -1

None

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

4 / 16 / 4.0

Contents of memory location address by the HL pair is compared to the contents of the accumulator.
Z is set if true otherwise reset,
S is set if result is negative otherwise reset,
H is set if borrow from bit 4 otherwise reset,
P/V is set if BC - 1 is not 0, reset otherwise,
N is set. HL is incremented, BC is decremented

CPIR - ComPare and Increment Repeat

The contents of the memory location addressed by the HL register is compared with the contents of the accumulator. If the compare is true, Z is set. HL is then incremented and the BC counter register pair (B and C) is decremented. This is repeated until A equals (HL) or until BC reaches 0, whichever comes first.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

CPIR

Source→ Dest↓	(HL)/th>
A	$(ED)B1

A

(HL)

A - (HL)
HL ← HL + 1
BC ← BC -1

None

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

A = (HL) or BC == 0
4 / 16 / 4.00
If A ≠ 0 and BC ≠ 0
5 / 21 / 5.25

Contents of memory location address by the HL pair is compared to the contents of the accumulator.
Z is set if true otherwise reset,
S is set if result is negative otherwise reset,
H is set if borrow from bit 4 otherwise reset,
P/V is set if BC - 1 is not 0, reset otherwise,
N is set. HL is incremented, BC is decremented. This operation is repeated until (HL) equals A or until BC reaches 0, whichever comes first.

CPL - ComPLement Accumulator

The contents of the Accumulator are inverted (one's complement).

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

CPL

Source→ Dest↓	A
A ← compl(A)	$2F

A

A ← compl(A)

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	-

1 / 4 / 1.0

Performs a one's complement on the Accumulator, inverting the bits.
H and N are set. S, Z, P/V and C are not affected.

DAA - Decimal Adjust Accumulator

Adjust the accumulator for BDC addition and subtraction. For BDC addition (add, adc, inc) or subtraction (sub, sbc, dec, neg) the following table indicates the operation that is performed, values are before the operation, unless otherwise noted.

Operation	Carry	Half Carry	Upper Nibble	Lower Nibble	Number added	Carry after
	0	0	9-0	0-9	00	0
	0	0	0-8	A-F	06	0
	0	1	0-9	0-3	06	0
	1	0	0-2	0-9	60	1
	1	0	0-2	A-F	66	1
	1	1	0-3	0-3	66	1
ADD	0	0	A-F	0-9	60	1
ADC	0	0	9-F	A-F	66	1
INC	0	1	A-F	0-3	66	1
SUB	0	0	0-9	0-9	00	0
SBC	0	1	0-8	6-F	FA	0
DEC	1	0	7-F	0-9	A0	1
NEG	1	1	6-7	6-F	9A	1

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

DAA

Source→ Dest↓	A
A ← @(A)	$27

A

@

A

S	Z	H	P/V	N	C
✓	✓	✓	✓	-	✓

1 / 4 / 1.0

Conditionally adjusts the Accumulator for BCD (Binary Coded Decimal) addition and subtraction operations. The table above shows how the accumulator is adjusted.
S is set if most-significant bit of the Accumulator is 1 after the operation, otherwise reset.
Z is set if Accumulator is 0 after the operation, otherwise reset.
H is set in accordance with the table above.
P/V is set if the Accumulator at even parity after the operation, reset otherwise.
N is not affected but the C bit is set according to the table above

DEC - DECrement

Performs a decrement of a register or memory address, with our without offset and sets flags accordingly.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

DEC r

Source→ Dest↓	A	B	C	D	E	H	L
DEC	$3D	$05	$0D	$15	$1D	$25	$2D

a,b,c,d,e,h or l

r

r ← r - 1

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

1 / 4 / 1.0

Decrements the register r.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if r was $80 before decrement, otherwise reset.
N is set, C is not affected

Register-Indirect-to-Implied

DEC (HL)

Source→ Dest↓	(HL)
DEC	$35

(HL)

(HL) ← (HL) - 1

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 11 / 2.75

Decrements the byte in memory pointed to by the HL register pair.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if r was $80 before decrement, otherwise reset.
N is set, C is not affected

Indexed-to-Implied

DEC (IX+d)

Source→ Dest↓	(IX+d)
DEC	$DD35d

(IX+d)

(IX+d) ← (IX+d) - 1

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

6 / 23 / 5.75

Decrements the byte stored at the memory address generated by adding the contents of the IX register to the two's complement displacement d.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if r was $80 before decrement, otherwise reset.
N is set, C is not affected

Indexed-to-Implied

DEC (IY+d)

Source→ Dest↓	(IY+d)
DEC	$FD35d

(IY+d)

(IY+d) ← (IY+d) - 1

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

6 / 23 / 5.75

Decrements the byte stored at the memory address generated by adding the contents of the IY register to the two's complement displacement d.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if r was $80 before decrement, otherwise reset.
N is set, C is not affected

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

DEC ss

Source→ Dest↓	BC	DE	HL	SP
DEC	$DB	$1B	$2B	$3B

ss

ss = (bc, de, hl, sp)

ss ← ss - 1

ss

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 6 / 1.50

Decrement the register pairs bc, de, hl or sp. No flags are set

Register

DEC IX

Source→ Dest↓	IX
DEC	$DD2B

IX

IX ← IX - 1

IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

Decrement Index Register X. No flags are set

Register

DEC IY

Source→ Dest↓	IY
DEC	$FD2B

IY

IY ← IY - 1

IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

Decrement Index Register Y. No flags are set

DI - Disable Interrupts

Disables the maskable interrupt by resetting the interrupt enable flip-flops (IFF1 and IFF2)

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

DI

Source→ Dest↓	DI
IFF=0	$F3

None

IFF ← 0

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.0

Disable the interrupts until re-enabled with a subsequent ei instruction. CPU will not respond to an INT request signal.

DJNZ - Decrement b and Jump if Not Zero

Decrement Register B, and while B is not 0, move the program counter (PC) e bytes relative of its current position. No flags are affected

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Relative

DJNZ e

Source→ Dest↓	e
PC=PC+e	$10e-2

PC

B, e

B ← B – 1
if B == 0, continue
if B ≠ 0
PC ← PC + e

e

S	Z	H	P/V	N	C
-	-	-	-	-	-

B ≠ 0
3 / 15 / 3.25
B == 0
2 / 8 / 2.00

Jump e bytes (-126 to +129) relative to the current PC if B ≠ 0. No flags are affected.

EI - Enable Interrupts

Enables the maskable interrupt by setting both the interrupt enable flip-flops (IFF1 and IFF2) to logic 1.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

EI

Source→ Dest↓	EI
IFF=1	$FB

IFF ← 1

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.0

Enable interrupts so that maskable interrupts can be received again.

EX - EXchange

Exchange the values of two registers.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied-to-Implied

EX DE, HL

Source→ Dest↓	HL/DE
DE/HL	$EB

DE, HL

DE ↔ HL

DE, HL

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.00

The contents of registers DE and HL have been swapped

Implied-to-Implied

EX AF, AF'

Source→ Dest↓	AF/AF'
AF'/AF	$08

AF'

AF ↔ AF'

AF, AF'

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.00

The contents of registers A and F have been swapped with their shadow register counterparts

Implied-to-Register-Indirect

EX (SP), HL

Source→ Dest↓	HL/(SP)
(SP)/HL	$E3

HL

(SP)

H ↔ (SP+1)
L ↔ (SP)

(SP), HL

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The low-order byte contained in register pair HL is exchanged with the contents of the memory address specified by the current stack pointer, and the high-order byte is exchanged with the contents of the memory address specified by SP+1.

Implied-to-Register-Indirect

EX (SP), IX

Source→ Dest↓	IX/(SP)
(SP)/IX	$DDE3

IX

(SP)

IXH ↔ (SP+1)
IXL ↔ (SP)

(SP), IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

The low-order byte contained in Index Register X is exchanged with the contents of the memory address specified by the current stack pointer, and the high-order byte is exchanged with the contents of the memory address specified by SP+1.

Implied-to-Register-Indirect

EX (SP), IY

Source→ Dest↓	IY/(SP)
(SP)/IY	$FDE3

IY

(SP)

IYH ↔ (SP+1)
IYL ↔ (SP)

(SP), IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

The low-order byte contained in Index Register Y is exchanged with the contents of the memory address specified by the current stack pointer, and the high-order byte is exchanged with the contents of the memory address specified by SP+1.

EXX - EXchange Shadow(X)

Exchange the values of registers to shadow registers. Exchanges the values of BC, DE and HL with their shadow register counterparts.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied-to-Implied

EXX

Source→ Dest↓	BC'/DE'/HL' BC/DE/HL
BC/DE/HL BC'/DE'/HL'	$D9

BC, DE, HL

BC', DE', HL'

BC ↔ BC'
DE ↔ DE'
HL ↔ HL'

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.00

The contents of registers BC, DE and HL have been swapped with their shadow register counterparts

HALT - HALT operations

Suspend CPU operations until an interrupt occurs or a reset is received. The CPU will execute NOP instructions to maintain memory refresh logic during this state. Executing a halt while interrupts are disabled is effectively a deadlock.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

None

HALT

Source→ Dest↓	HALT
HALT	$76

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.0

Halt until an interrupt or reset is received.

IM - Interrupt Mode

Sets the interrupt mode to a value between 0-2.

Mode	Operation
0	The interrupting device can insert any instruction on the data bus for execution by the CPU. The first byte of the multi-byte instruction is read during the interrupt acknowledgement cycle. Subsequent bytes are read in by a normal memory read sequence.
1	The processor responds to an interrupt by executing a restart at address $0038
2	Sets vectored interrupt mode 2. This mode allows an indirect call to any memory location by an 8-bit vector supplied from the peripheral device. This vector then becomes the least-significant eight bits of an indirect pointer while the I register in the CPU provides the most-significant eight bits. This address points to an address in a vector-table that is the starting address for the interrupt service routine.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

IM n

Source→ Dest↓	n=0	n=1	n=2
Interrupt Mode = n	$ED46	$ED56	$ED5E

None

IM == n

n

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 8 / 2.0

Enable interrupt mode in accordance with the table above.

IN - INput

Reads input from a selected I/O device into a register.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Immediate-to-Register

IN A, (n)

Source→ Dest↓	I/O device (n)
A	$DBn

A

(n)

A ← (n)

A, (n)

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 11 / 2.75

The operand n is placed on the bottom half (A0 to 7) of the Address bus to select the I/O device at one of the 256 possible ports. The contents of the Accumulator appear on the upper half (A8-A15) of the address bus at the same time. One byte from the selected I/O port (signified by n) is placed on the data bus and read into the Accumulator.

Register-Indirect-to-Register

IN r, (C)

Source→ Dest↓	I/O device (C)
A	$ED78
B	$ED40
C	$ED48
D	$ED50
E	$ED58
H	$ED60
L	$ED68

r = (a, b, c, d, e, h, l)

(C)

r ← (C)

r,(C)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 12 / 3.00

The contents of register C is placed on the bottom half (A0-A7) of the address bus to select the I/O device at one of the 256 possible ports. The contents of register B are placed on the top half (A8 to A15) of the address bus at the same time. One byte from the selected port is then placed into register r in the CPU. Register r can be selected from a list of a, b, c, d, e, h and l.
S is set if input data is negative, otherwise reset
Z is set if input data is 0, otherwise reset
H and N are reset
P/V is set if parity is even, reset otherwise
C is not affected

IND - INput into memory with Decrement

Read a byte from I/O device number indicated by the byte in register C into memory at address pointed to be the HL register pair. The B register is decremented when a byte is read and the memory address pointed to by HL is decremented by one.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

IND

Source→ Dest↓	I/O device (C)
(HL)	$EDAA

(HL)

(C)

(HL) ← (C)
B ← B - 1
HL ← HL ö 1

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

4 / 16 / 4.00

The contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B can be used as a byte counter, and is placed at the higher part of the bus (A8-A15) at the same time. One byte from the selected port is then placed on the data bus and written to the CPU. The contents of the HL register pair are then placed on the address bus and the value is written to memory where they point. Finally the byte counter is decremented and the register pair HL is decremented.
Z is set if B-1 = 0, otherwise reset
S, H, P/V are unknown, N is set, C is not affected.

INDR - INput into memory with Decrement and Repeat

Read a byte from I/O device number indicated by the byte in register C into memory at address pointed to be the HL register pair. The B register is decremented when a byte is read and the memory address pointed to by HL is decremented by one. This operation is then repeated until the B == 0.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

INDR

Source→ Dest↓	I/O device (C)
(HL)	$EDBA

(HL)

(C)

While
(B ≠ 0) {
(HL) ← (C)
B ← B - 1
HL ← HL - 1
}

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

B ≠ 0
5 / 21 / 5.25
B == 0
4 / 16 / 4.00

The contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B can be used as a byte counter, and is placed at the higher part of the bus (A8-A15) at the same time. One byte from the selected port is then placed on the data bus and written to the CPU. The contents of the HL register pair are then placed on the address bus and the value is written to memory where they point. Finally the byte counter is decremented and the register pair HL is decremented. This operation is then repeated until B == 0. Interrupts are recognized and two refresh cycles are executed after each transfer.
Z and N are set, S, H and P/V are unknown, C is not affected

INI - INput into memory with Increment

Read a byte from I/O device number indicated by the byte in register C into memory at address pointed to be the HL register pair. The B register is decremented when a byte is read and the memory address pointed to by HL is incremented by one.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

INI

Source→ Dest↓	I/O device (C)
(HL)	$EDA2

(HL)

(C)

(HL) ← (C)
B ← B - 1
HL ← HL + 1

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

4 / 16 / 4.00

The contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B can be used as a byte counter, and is placed at the higher part of the bus (A8-A15) at the same time. One byte from the selected port is then placed on the data bus and written to the CPU. The contents of the HL register pair are then placed on the address bus and the value is written to memory where they point. Finally the byte counter is decremented and the register pair HL is incremented.

INIR - INput into memory and Increment Repeat

Read a byte from I/O device number indicated by the byte in register C into memory at address pointed to be the HL register pair. The B register is decremented when a byte is read and the memory address pointed to by HL is incremented by one. The operation is repeated until B == 0. 256 bytes can be read by starting with B = 0, it is then decremented 256 times. Interrupts are recognized and two refresh cycles execute after each data transfer.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

INIR

Source→ Dest↓	I/O device (C)
(HL)	$EDB2

(HL)

(C)

while
( B ≠ 0 ) {
(HL) ← (C)
B ← B - 1
HL ← HL + 1 }

None

S	Z	H	P/V	N	C
?	✓	?	?	✓	-

If B ≠ 0
5 / 21 / 5.25
If B == 0
4 / 16 / 4.00

The contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B which is used as a byte counter, is then placed at the higher part of the bus (A8-A15) at the same time. One byte from the selected port is then placed on the data bus and written to the CPU. The contents of the HL register pair are then placed on the address bus and the value is written to memory where they point. Finally the byte counter is decremented and the register pair HL is incremented. The operation is then repeated until B bytes (or if B=0, 256 bytes) have been read, allowing two refresh cycles and interrupt service between executions.
S, H and P/V are unknown, Z and N are set, C is unaffected.

INC - INCrement

Performs an increment of a register or memory address, with our without offset and sets flags accordingly.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-implied

INC r

Source→ Dest↓	A	B	C	D	E	H	L
INC	$3C	$04	$0C	$14	$1C	$24	$2C

a,b,c,d,e,h or l

r

r ← r + 1

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

1 / 4 / 1.0

Increments the register r.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if r is $7F before increment, otherwise reset.
N is reset, C is not affected

Register-Indirect-to-Implied

INC (HL)

Source→ Dest↓	(HL)
INC	$34

(HL)

(HL) ← (HL) + 1

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 11 / 2.75

Increments the byte in memory pointed to by the HL register pair.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if r is $7F before increment, otherwise reset.
N is reset, C is not affected

Indexed-to-Implied

INC (IX+d)

Source→ Dest↓	(IX+d)
INC	$DD34d

(IX+d)

(IX+d) ← (IX+d) + 1

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

6 / 23 / 5.75

Increments the byte stored at the memory address generated by adding the contents of the IX register to the two's complement displacement d.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if r is $7F before increment, otherwise reset.
N is reset, C is not affected

Indexed-to-Implied

INC (IY+d)

Source→ Dest↓	(IY+d)
INC	$FD34d

(IY+d)

(IY+d) ← (IY+d) + 1

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

6 / 23 / 5.75

Increments the byte stored at the memory address generated by adding the contents of the IY register to the two's complement displacement d.
S is set if result is negative, otherwise reset.
Z is set if result is zero, otherwise reset.
H is set if carry from bit 3, otherwise reset.
P/V is set if r is $7F before increment, otherwise reset.
N is reset, C is not affected

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

INC ss

Source→ Dest↓	BC	DE	HL	SP
INC	$03	$13	$23	$33

ss

ss = (bc, de, hl, sp)

ss ← ss + 1

ss

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 6 / 1.50

Increment the register pairs bc, de, hl or sp. No flags are set

Register

INC IX

Source→ Dest↓	IX
INC	$DD23

IX

IX ← IX + 1

IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

Increment Index Register X. No flags are set

Register

INC IY

Source→ Dest↓	IY
INC	$FD23

IY

IY ← IY + 1

IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

Increment Index Register Y. No flags are set

JP - JumP

Move the program counter (PC) to the location specified by nn or memory location, either with or without checking a condition flag. The following table shows the conditions possible and their relevant flags.

Condition	Flag
Sign-Positive (P)	S
Sign-Negative (N)	S
Non-Zero (NZ)	Z
Zero (Z)	Z
Parity-Odd (PO)	P/V
Parity-Even (PE)	P/V
No-Carry (NC)	C
Carry (C)	C

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Immediate-Extended

JP nn

Source→ Dest↓	nn
PC	$C3nn

PC

nn

PC ← nn

nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 10 / 2.50

Move the PC and jump to the location specified in nn, first byte being the lower byte of the address.
No flags are affected

Immediate-Extended

JP cc, nn

Source→ Dest↓	NZ, nn	Z, nn	NC, nn	C, nn	PO, nn	PE, nn	P, nn	M, nn
PC	$C2nn	$CAnn	$D2nn	$D8nn	$E2nn	$E8nn	$F2nn	$F8nn

PC

nn, cc=(NZ, Z, NC, C, PO, PE, P, M)

IF cc true, PC ← nn

nn,cc

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 10 / 2.50

Move the PC and jump to the location specified in nn, first byte being the lower byte of the address.
No flags are affected

Register-Indirect

JP (HL)

Source→ Dest↓	(HL)
PC	$EB

PC

(HL)

PC ← (HL)

(HL)

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.00

Move the PC and jump to the location specified by the 16-bit value pointed to by the HL register pairnn.
No flags are affected

Register-Indirect

JP (IX)

Source→ Dest↓	(IX)
PC	$DDE9

PC

(IX)

PC ← (IX)

(IX)

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.00

Move the PC and jump to the location specified by the 16-bit value pointed to by the Index register X.
No flags are affected

Register-Indirect

JP (IY)

Source→ Dest↓	(IY)
PC	$FDE9

PC

(IY)

PC ← (IY)

(IY)

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 8 / 2.00

Move the PC and jump to the location specified by the 16-bit value pointed to by the Index register Y.
No flags are affected

JR - Jump Relative

Move the program counter (PC) to a location relative of the current program counter, either with or without a conditional check. Conditional checks are listed in the following table.

Condition	Flag
Non-Zero (NZ)	Z
Zero (Z)	Z
No-Carry (NC)	C
Carry (C)	C

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Relative

JR e

Source→ Dest↓	e
PC=PC+e	$18e-2

PC

e

PC ← PC + e

e

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 12 / 3.00

Jupm e bytes, from -126 to +129, from the current PC location unconditionally.

Relative

JR C, e

Source→ Dest↓	C, e
PC=PC+e	$38e-2

PC

C, e

IF C true, PC ← PC + e

C, e

S	Z	H	P/V	N	C
-	-	-	-	-	-

Flag True
3 / 12 / 3.00
Flag false
2 / 7 / 1.75

Jump e bytes, from -126 to +129, if Carry is set.
No flags are affected

Relative

JR NC, e

Source→ Dest↓	NC, e
PC=PC+e	$30e-2

PC

NC, e

IF NC true, PC ← PC + e

NC, e

S	Z	H	P/V	N	C
-	-	-	-	-	-

Flag True
3 / 12 / 3.00
Flag false
2 / 7 / 1.75

Jump e bytes, from -126 to +129, if NC is 1 (Carry is 0).
No flags are affected

Relative

JR Z, e

Source→ Dest↓	Z, e
PC=PC+e	$28e-2

PC

Z, e

IF Z true, PC ← PC + e

Z, e

S	Z	H	P/V	N	C
-	-	-	-	-	-

Flag True
3 / 12 / 3.00
Flag false
2 / 7 / 1.75

Jump e bytes, from -126 to +129, if Z is 1 (Zero flag is set).
No flags are affected

Relative

JR NZ, e

Source→ Dest↓	NZ, e
PC=PC+e	$28e-2

PC

NZ, e

IF NZ true, PC ← PC + e

NZ, e

S	Z	H	P/V	N	C
-	-	-	-	-	-

Flag True
3 / 12 / 3.00
Flag false
2 / 7 / 1.75

Jump e bytes, from -126 to +129, if NZ is 1 (Zero flag is 0).
No flags are affected

LD - LoaD instructions for 8-bit values

Load register or memory with data from register, memory or absolute value, with our without displacement

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register

LD r, r'

Source→ Dest↓	A	B	C	D	E	H	L
A	$7F	$78	$79	$7A	$7B	$7C	$7D
B	$47	$40	$41	$42	$43	$44	$45
C	$4F	$48	$49	$4A	$4B	$4C	$4D
D	$57	$50	$51	$52	$53	$54	$55
E	$5F	$58	$59	$5A	$5B	$5C	$5D
H	$67	$60	$61	$62	$63	$64	$65
L	$6F	$68	$69	$6A	$6B	$6C	$6D

r = (a, b, c, d, e, h, l)

r' = (a, b, c, d, e, h, l)

r ← r′

r, r'

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.0

The contents of register r' are placed into register r

Immediate-to-Register

LD r, n

Source→ Dest↓	n
A	$3E
B	$06
C	$0E
D	$16
E	$1E
H	$26
L	$2E

r= (a, b, c, d, e, h, l)

n

r ← n

r, n

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of integer n are placed into register r

Register-Indirect-to-Register

LD r, (HL)

Source→ Dest↓	(HL)
A	$7E
B	$46
C	$4E
D	$56
E	$5E
H	$66
L	$6E

r = (a, b, c, d, e, h, l)

(HL)

r ← (HL)

r, (HL)

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of memory specified by the HL pair are transfered into register r

Indexed-to-Register

LD r, (IX+d)

Source→ Dest↓	(IX+d)
A	$DD7E
B	$DD46
C	$DD4E
D	$DD56
E	$DD5E
H	$DD66
L	$DD6E

r = (a, b, c, d, e, h, l)

(IX+d)

r, ← (IX+d)

r, (IX+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The contents of IX summed with displacment d is loaded to register r

Indexed-to-Register

LD r, (IY+d)

Source→ Dest↓	(IY+d)
A	$FD7E
B	$FD46
C	$FD4E
D	$FD56
E	$FD5E
H	$FD66
L	$FD6E

r = (a, b, c, d, e, h, l)

(IY+d)

r, ← (IY+d)

r, (IY+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The contents of IY summed with displacment d is loaded to register r

Register-to-Register-Indirect

LD (HL), r

Source→ Dest↓	A	B	C	D	E	F	L
(HL)	$77	$70	$71	$72	$73	$74	$75

(HL)

r = (a, b, c, d, e, h, l)

(HL) ← r

(HL), r

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of register r are loaded into the location specified by the HL pair

Register-to-Indexed

LD (IX+d), r

Source→ Dest↓	A	B	C	D	E	F	L
(IX+d)	$DD77	$DD70	$DD71	$DD72	$DD73	$DD74	$DD75

(IX+d)

a, b, c, d, e, h, l

(IX+d) ← r

(IX+d), r

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The contents of register r are load into the location specified by IX summed with displacement d

Register-to-Indexed

LD (IY+d), r

Source→ Dest↓	A	B	C	D	E	F	L
(IY+d)	$FD77	$FD70	$FD71	$FD72	$FD73	$FD74	$FD75

(IY+d)

a, b, c, d, e, h, l

(IY+d) ← r

(IY+d), r

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The contents of register r are loaded into the location specified by IY summed with displacement d

Immediate-to-Register-Indirect

LD (HL), n

Source→ Dest↓	n
(HL)	$36

(HL)

n

(HL) ← n

(HL), n

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 10 / 2.5

The integer n is loaded to the memory address specified by the HL pair

Immediate-to-Indexed

LD (IX+d), n

Source→ Dest↓	n
(IX+d)	$DD36

(IX+d)

n

(IX+d) ← n

(IX+d), n

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The integer n is loaded to the memory address specified by the IX summed with displacement d

Immediate-to-Indexed

LD (IY+d), n

Source→ Dest↓	n
(IY+d)	$FD36

(IY+d)

n

(IY+d) ← n

(IY+d), n

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 19 / 4.75

The integer n is loaded to the memory address specified by the IY summed with displacement d

Register-Indirect-to-Register

LD A, (BC)

Source→ Dest↓	(BC)
A	$0A

A

(BC)

A ← (BC)

A, (BC)

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

Load the accumulator with the contents of the memory location specified by the contents of the BC register pair

Register-Indirect-to-Register

LD A, (DE)

Source→ Dest↓	(DE)
A	$1A

A

(DE)

A ← (DE)

A, (DE)

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

Load the accumulator with the contents of the memory location specified by the contents of the DE register pair

Extended-to-Register

LD A, (nn)

Source→ Dest↓	(nn)
A	$3A

A

(nn)

A ← (nn)

A, (nn)

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 13 / 3.25

Load the accumulator with the contents of the memory location specified by the operand nn, where former is the lower byte and latter is the higher byte

Register-to-Register-Indirect

LD (BC), A

Source→ Dest↓	A
(BC)	$02

(BC)

A

(BC) ← A

(BC), A

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of the accumulator are stored at the memory location pointed to by the (BC) register pair

Register-to-Register-Indirect

LD (DE), A

Source→ Dest↓	A
(DE)	$12

(DE)

A

(DE) ← A

(DE), A

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of the accumulator are stored at the memory location pointed to by the (DE) register pair

Register-to-Extended

LD (nn), A

Source→ Dest↓	A
(nn)	$32

(nn)

A

(nn) ← A

(nn), A

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 7 / 1.75

The contents of the accumulator are stored at the memory location pointed to by the operands n and n

Implied-to-Register

LD A, I

Source→ Dest↓	I
A	$ED57

A

I

A ← I

A, I

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 9 / 2.25

The contents of the Interrupt Vector Register are loaded into the accumulator

Implied-to-Register

LD A, R

Source→ Dest↓	R
A	$ED5F

A

R

A ← R

A, R

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 9 / 2.25

The contents of the Memory Refresh Register are loaded into the accumulator

Register-to-Implied

LD I, A

Source→ Dest↓	A
I	$ED47

I

A

I ← A

I, A

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 9 / 2.25

The contents of the accumulator are loaded into the Interrupt Vector Register

Register-to-Implied

LD R, A

Source→ Dest↓	A
R	$ED4F

R

A

R ← A

R, A

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 9 / 2.25

The contents of the accumulator are loaded into the Memory Refresh Register

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Immediate-extended-to-Register

LD dd, nn

Source→ Dest↓	nn
BC	$01
DE	$11
HL	$21
SP	$31

dd = (bc, de, hl, sp)

nn

dd ← nn

dd, nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

The 2-byte integer nn is loaded into the dd register pair bc, de, hl or sp, high order into the first register, low order into the second one. The nn are in low order, high order.

Immediate-extended-to-Register

LD IX, nn

Source→ Dest↓	nn
IX	$DD21

IX

nn

IX ← nn

IX, nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

The 2-byte integer nn is loaded into Index register X, in low order, high order order

Immediate-extended-to-Implied

LD IY, nn

Source→ Dest↓	nn
IY	$FD21

IY

nn

IY ← nn

IY, nn

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

The 2-byte integer nn is loaded into Index register Y, in low order, high order order

Extended-to-Register

LD HL, (nn)

Source→ Dest↓	(nn)
HL	$2A

HL

(nn)

H, ← (nn+1)
L ← (nn)

HL, (nn)

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 16 / 4.00

The contents of memory address pointed to by nn is loaded in L and high order byte pointed to by NN is loaded into H, the low order byte of the memory address is specified first

Extended-to-Register

LD dd, (nn)

Source→ Dest↓	(nn)
BC	$ED4B
DE	$ED5B
HL	$2A
SP	$ED7B

dd = (BC, DE, HL, SP)

(nn)

ddh ← (nn+1)
ddl, ← (nn)

dd, (nn)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of memory address pointed to by nn is loaded into register pairs BC, DE, HL or SP. The low order byte of the memory address is specified first

Extended-to-Register

LD IX, (nn)

Source→ Dest↓	(nn)
IX	$DD2A

IX

(nn)

IXh ← (nn+1)
IXi ← (nn)

IX, (nn)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of the address pointed to by nn are loaded into the low and high portion of Index register X, the first operand is the low byte

Extended-to-Register

LD IY, (nn)

Source→ Dest↓	(nn)
IY	$FD2A

IY

(nn)

IYh ← (nn+1)
IYi ← (nn)

IY, (nn)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of the address pointed to by nn are loaded into the low and high portion of Index register Y, the first operand is the low byte

Register-to-Extended

LD (nn), HL

Source→ Dest↓	HL
(nn)	$22

(nn)

HL

(nn+1) ← H
(nn) ← L

(nn), HL

S	Z	H	P/V	N	C
-	-	-	-	-	-

5 / 16 / 4.00

The contents of register L is loaded into memory address nn, and the contents of register H is loaded into memory address nn+1, The first n operand is the low order byte of nn

Register-to-Extended

LD (nn), dd

Source→ Dest↓	bc	de	hl	sp
(nn)	$ED43	$ED53	$22	$ED73

(nn)

dd

(nn+1) ← ddh
(nn) ← ddl

(nn), dd

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of register ddh is loaded into memory address nn, and the contents of register ddl is loaded into memory address nn+1

Register-to-Extended

LD (nn), IX

Source→ Dest↓	IX
(nn)	$DD22

(nn)

IX

(nn+1) ← IXh
(nn) ← IXl

(nn), IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of register IX are loaded into the location specified by nn, the first n operand being the lower byte of nn

Register-to-Extended

LD (nn), IY

Source→ Dest↓	IY
(nn)	$FD22

(nn)

IY

(nn+1) ← IYh
(nn) ← IYl

(nn), IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 20 / 5.00

The contents of register IY are loaded into the location specified by nn, the first n operand being the lower byte of nn

Register-to-Register

LD SP, HL

Source→ Dest↓	HL
SP	$F9

SP

HL

SP ← HL

SP, HL

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 6 / 1.50

The contents of the register pair HL are moved to the stack pointer

Register-to-Register

LD SP, IX

Source→ Dest↓	IX
SP	$DDF9

SP

IX

SP ← IX

SP, IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

The 2 byte contents of index register X are moved to the stack pointer

Register-to-Register-Indirect

LD SP, IY

Source→ Dest↓	IY
SP	$FDF9

SP

IY

SP ← IY

SP, IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

2 / 10 / 2.50

The 2 byte contents of index register Y are moved to the stack pointer

LDD - LoaD and Decrement

Transfer a byte of data from the memory location addressed by the HL register pair to the memory location address by the contents of the DE register pair. Then both HL and DE are decremented and then the BC (Byte counter) register is decremented. This is essentially a stack copy operation from HL to DE, with an auto-decrement for the 4 registers in addition to a decrement for the byte-counter.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-indirect-to-Register-indirect

LDD

Source→ Dest↓	(HL)
(DE)	$(ED)A8

(DE)

(HL)

(DE) ← (HL)
DE ← DE - 1
HL ← HL - 1
BC ← BC -1

None

S	Z	H	P/V	N	C
-	-	✓	✓	✓	-

4 / 16 / 4.0

Memory pointed to by HL is moved to memory pointed to by DE, DE is decremented, HL is decremented, BC is decremented.
H is reset. P/V is set if BC -1 is not 0, otherwise reset, N is reset.

LDI - LoaD and Increment

Transfer a byte of data from the memory location addressed by the HL register pair to the memory location address by the contents of the DE register pair. Then both HL and DE are incremented and the BC (Byte counter) register is decremented. This is essentially a copy operation from HL to DE, with an auto-increment for the 4 registers and a decrement for the byte-counter.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Register-Indirect

LDI

Source→ Dest↓	(HL)
(DE)	$(ED)A0

(DE)

(HL)

(DE) ← (HL)
DE ← DE + 1
HL ← HL + 1
BC ← BC -1

None

S	Z	H	P/V	N	C
-	-	✓	✓	✓	-

4 / 16 / 4.0

Memory pointed to by HL is moved to memory pointed to by DE, DE is incremented, HL is incremented, BC is decremented.
H is reset. P/V is set if BC -1 is not 0, otherwise reset. N is reset.

LDDR - LoaD and Decrement Repeat

Transfer a byte of data from the memory location addressed by the HL register pair to the memory location address by the contents of the DE register pair. Then both HL and DE are decremented and the BC (Byte counter) register is decremented. This continues until BC reaches 0. This is essentially a stack memory copy of BC bytes from HL to DE.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Register-Indirect

LDDR

Source→ Dest↓	(HL)
(DE)	$(ED)B8

(DE)

(HL)

repeat {
(DE) ← (HL)
DE ← DE - 1
HL ← HL - 1
BC ← BC -1 }
while (BC ≠ 0)

None

S	Z	H	P/V	N	C
-	-	✓	✓	✓	-

(BC ≠ 0) 5/21/5.25
(BC == 0) 4/16/4.00

Memory pointed to by HL is moved to memory pointed to by DE, DE is decremented, HL is decremented, BC is decremented. This is repeated until BC == 0. H, P/V and N are reset

LDIR - LoaD and Increment Repeat

Transfer a byte of data from the memory location addressed by the HL register pair to the memory location address by the contents of the DE register pair. Then both HL and DE are incremented and the BC (Byte counter) register is decremented. This continues until BC reaches 0. This is essentially a memory copy of BC bytes from HL to DE.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Register-Indirect

LDIR

Source→ Dest↓	(HL)
(DE)	$(ED)B0

(DE)

(HL)

repeat {
(DE) ← (HL)
DE ← DE + 1
HL ← HL + 1
BC ← BC -1 }
while (BC ≠ 0)

None

S	Z	H	P/V	N	C
-	-	✓	✓	✓	-

(BC ≠ 0) 5/21/5.25
(BC == 0) 4/16/4.00

Memory pointed to by HL is moved to memory pointed to by DE, DE is incremented, HL is incremented, BC is decremented. This is repeated until BC == 0.
H is reset, P/V is set if BC -1 is not 0, otherwise reset. N is reset.

NEG - NEGate Accumulator

The contents of the Accumulator are negated (two's complement). This method is the same as subtracting the contents of the Accumulator from Zero.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

NEG

Source→ Dest↓	A
A ← 0 - A	$ED44

A

A ← 0 - A

None

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Negates the accumulator.
S is set if result is negative, reset otherwise.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if Accumulator was $80 before operation, otherwise reset.
N is set, C is set if Accumulator was not $00 before operation, otherwise reset

NOP - No OPeration

The processor does nothing during the execution of this opcode.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

None

NOP

Source→ Dest↓	NOP
NOP	$00

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

1 / 4 / 1.0

Do nothing. No flags are affected.

OTDR - OuTput from memory with Decrement Repeat

Write a byte to I/O device number indicated by the byte in register C from memory at address pointed to be the HL register pair. The B register is decremented when a byte is written and the memory address pointed to by HL is decremented by one. This is repeated until B == 0.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

OTDR

Source→ Dest↓	(HL)
I/O device (c)	$EDB8

(C)

(HL)

while B ≠ 0 {
(C) ← (HL)
B ← B - 1
HL ← HL ö 1 }

(C), (HL)

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

If B ≠ 0
5 / 21 / 5.25
If B == 0
4 / 16 / 4.00

The contents of the HL register pair are placed on the address bus to select the location in memory. THe byte contained at that memory location is then temporarily stored in the CPU. The byte counter at B is decremented and then the contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B which can be used as a byte counter and has already been decremented, is placed at the higher part of the bus (A8-A15) at the same time. The byte to be output is then placed on the data bus and written to the selected I/O device. Finally the register pair HL is decremented. This is repeated until B == 0. Interrupts are recognized and two refresh cycles are executed after each data transfer.
S, H, P/V are unknown, Z and N are set, C is not affected

OUT - OUTput

Outputs a register to a selected I/O device

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Immediate

OUT (n), A

Source→ Dest↓	A
I/O device(n)	$D3n

(n)

A

(n) ← (A)

(n),A

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 11 / 2.75

The operand n is placed on the bottom half (A0 to 7) of the Address bus to select the I/O device at one of the 256 possible ports. The contents of the Accumulator appear on the upper half (A8-A15) of the address bus at the same time. Then the byte from the Accumulator is written to the selected I/O device. No flags are affected

Register-to-Immediate

OUT r, (C)

Source→ Dest↓	A	B	C	D	E	H	L
I/O device (C)	$ED79	$ED41	$ED49	$ED51	$ED59	$ED61	$ED69

(C)

r = (a, b, c, d, e, h, l)

(C) ← (r)

(C), r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	-

3 / 12 / 3.00

The contents of register C is placed on the bottom half (A0-A7) of the address bus to select the I/O device at one of the 256 possible ports. The contents of register B are placed on the top half (A8 to A15) of the address bus at the same time. The byte contained in register r is written to the selected I/O device.
No flags are affected

OUTD - OUTput from memory with Decrement

Write a byte to I/O device number indicated by the byte in register C from memory at address pointed to be the HL register pair. The B register is decremented when a byte is written and the memory address pointed to by HL is decremented by one.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

OUTD

Source→ Dest↓	(HL)
I/O device (c)	$EDA8

(C)

(HL)

(C) ← (HL)
B ← B - 1
HL ← HL ö 1

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

4 / 16 / 4.00

The contents of the HL register pair are placed on the address bus to select the location in memory. THe byte contained at that memory location is then temporarily stored in the CPU. The byte counter at B is decremented and then the contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B which can be used as a byte counter and has already been decremented, is placed at the higher part of the bus (A8-A15) at the same time. The byte to be output is then placed on the data bus and written to the selected I/O device. Finally the register pair HL is decremented.
Z is set if B-1 = 0, otherwise reset
S, H, P/V are unknown, N is set, C is not affected.

OUTI - OUTput from memory with Increment

Write a byte to I/O device number indicated by the byte in register C from memory at address pointed to be the HL register pair. The B register is decremented when a byte is written and the memory address pointed to by HL is incremented by one.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

OUTI

Source→ Dest↓	(HL)
I/O device (c)	$EDA3

(C)

(HC

(C) ← (HL)
B ← B - 1
HL ← HL + 1

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

4 / 16 / 4.00

The contents of the HL register pair are placed on the address bus to select a locatio in memory. The byte contained in that memory location is then stored temporarily in the CPU. After the byte counter B is decremented, the contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B which can be used as a byte counter and whose value has already been decremented, is placed at the higher part of the bus (A8-A15) at the same time. The byte to output is placed on the data bus and is written to the selected I/O device. Finally the register pair HL is incremented by one.
Z is set if B -1 = 0, otherwise reset
S, H and P/V are unknown, N is set, C is not affected

OTIR - OutPut from memory with Increment Repeat

Write a byte to I/O device number indicated by the byte in register C from memory at address pointed to be the HL register pair. The B register is decremented when a byte is written and the memory address pointed to by HL is incremented by one. The operation is continued until B == 0. Note that 256 bytes can be read by setting B = 0 at the start of the operation.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Implied

OTIR

Source→ Dest↓	(HL)
I/O device (c)	$EDB3

(C)

(HC

While B ≠ 0 {
(C) ← (HL)
B ← B - 1
HL ← HL + 1 }

None

S	Z	H	P/V	N	C
✓	✓	?	?	✓	-

If B ≠ 0
5 / 21 / 5.25
If B == 0
4 / 16 / 4.00

The contents of the HL register pair are placed on the address bus to select a locatio in memory. The byte contained in that memory location is then stored temporarily in the CPU. After the byte counter B is decremented, the contents of register C are placed on the bottom half (A0-A7) of the address bus to select the I/O device from a choice of 256 devices. Register B which can be used as a byte counter and whose value has already been decremented, is placed at the higher part of the bus (A8-A15) at the same time. The byte to output is placed on the data bus and is written to the selected I/O device. Finally the register pair HL is incremented by one. This is repeated until B == 0. Interrupts are recognized and two refresh cycles are executed after each data transfer.
Z is set if B -1 = 0, otherwise reset
S, H and P/V are unknown, N is set, C is not affected

OR - Perform logical OR with accumulator

Perform a logical OR operation between a register, integer or memory address, with or without offset, to the accumulator and store the result in the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to_Implied

OR r

Source→ Dest↓	A	B	C	D	E	H	L
OR	$B7	$B0	$B1	$B2	$B3	$B4	$B5

A

a, b, c, d, e, h, l

A ← A ˅ r

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

A logical OR operation is performed between the contents of r and the accumulator and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Immediate-to-Implied

OR n

Source→ Dest↓	n
OR	$F6n

A

n

A ← A ˅ n

A, n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical OR operation is performed between the integer n and the contents of the Accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Register-Indirect-to-Implied

OR (HL)

Source→ Dest↓	(HL)
OR	$B6

A

(HL)

A ← A ˅ (HL)

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical OR operation is performed between the byte at the address pointed to by the HL register pair and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

OR (IX+d)

Source→ Dest↓	(IX+d)
OR	$DDB6d

A

(IX+d)

A ← A ˅ (IX+d)

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical OR operation is performed between the byte at the address generated by adding the contents of the IX register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

OR (IX+d)

Source→ Dest↓	(IX+d)
OR	$FDB6d

A

(IY+d)

A ← A ˅ (IY+d)

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical OR operation is performed between the byte at the address generated by adding the contents of the IY register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator to the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

POP - POP registers from stack

Pop register pair from the LIFO stack. First the low order byte is fetched from SP, then the SP is incremented by 1, and the high order byte is fetched from SP+1, then the stack pointer is incremented again and ends up as SP+2

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect-to-Register

POP qq

Source→ Dest↓	(SP)
BC	$C1
DE	$D1
HL	$E1
AF	$B1

qq = (BC, DE, HL, AF)

Stack

qqL, ← (SP)
qqh ← (SP+1)
SP+2

qq

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 10 / 2.50

Pop the contents of registers BC, DE, HL or AF from the stack, low order first

Register-Indirect-to-Register

POP IX

Source→ Dest↓	(SP)
IX	$DDE1

IX

Stack

IXL, ← (SP)
IXH ← (SP+1)
SP+2

IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

Pop the contents of Index Register X from the stack, low order first

Register-Indirect-to-Register

POP IY

Source→ Dest↓	(SP)
IY	$FDE1

IY

Stack

IYL, ← (SP)
IYH ← (SP+1)
SP+2

IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

Pop the contents of Index Register Y from the stack, low order first

PUSH - PUSH registers to stack

Push registers to the LIFO stack. The Stack pointer (SP) Register holds the 16-bit address of the current top of stack. The instruction decrements SP and loads the high-order byte of register pair SP-1, then decrements SP again and loads the low order byte to SP-2.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register-indirect

PUSH qq

Source→ Dest↓	BC	DE	HL	AF
(SP)	$C6	$D6	$E6	$F6

Stack

qq = (BC, DE, HL, AF)

(SP-2), ← qqL
(SP-1) ← qqH

qq

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 11 / 2.75

The contents of registers BC, DE, HL or AF have been pushed to the stack

Register-to-Register-Indirect

PUSH IX

Source→ Dest↓	IX
(SP)	$DDE6

Stack

IX

(SP-2), ← IXL, (SP-1) ← IXH

IX

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 15 / 3.75

The contents of index register X has been pushed to the stack

Register-to-Register-Indirect

PUSH IY

Source→ Dest↓	IY
(SP)	$FDE6

Stack

IY

(SP-2), ← IYL, (SP-1) ← IYH

IY

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 15 / 3.75

The contents of index register Y has been pushed to the stack

RES - RESet bit

Reset a bit in register or memory, with or without offset.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

RES b, r

Source→ Dest Bit↓	A	B	C	D	E	H	L
0	$C887	$C880	$C881	$C882	$C883	$C884	$C885
1	$C88F	$C888	$C889	$C88A	$C88B	$C88C	$C88D
2	$C897	$C890	$C891	$C892	$C893	$C894	$C895
3	$C89F	$C898	$C899	$C89A	$C89B	$C89C	$C89D
4	$C8A7	$C8A0	$C8A1	$C8A2	$C8A3	$C8A4	$C8A5
5	$C8AF	$C8A8	$C8A9	$C8AA	$C8AB	$C8AC	$C8AD
6	$C8B7	$C8B0	$C8B1	$C8B2	$C8B3	$C8B4	$C8B5
7	$C8BF	$C8B8	$C8B9	$C8BA	$C8BB	$C8BC	$C8BD

r=(a,bc,d,e,h,l)b

b

rb ← 0

b, r

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 8 / 2.00

Resets bit b of register r (sets it to 0).
No flags are affected

Register-Indirect

RES b, (HL)

Source→ Dest Bit↓	(HL)
0	$C886
1	$C88E
2	$C896
3	$C89E
4	$C8A6
5	$C8AE
6	$C8B6
7	$C8BE

(HL)b

b

(HL)b ← 1

b, (HL)

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 15 / 3.75

Resets bit b of the byte pointed to by memory location stored in register pair HL. (Sets it to 0).
No falgs are affected.

Indexed

RES b, (IX+d)

Source→ Dest Bit↓	(IX+d)
0	$DDC8d86
1	$DDC8d8E
2	$DDC8d96
3	$DDC8d9E
4	$DDC8dA6
5	$DDC8dAE
6	$DDC8dB6
7	$DDC8dBE

(IX+d)b

b

(IX+d)b ← 1

b, (IX+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

Resetst bit b of the byte stored at the memory address generated by adding the contents of the IX register to the two's complement displacement d. (Sets it to 0)
No flags are affected

Indexed

RES b, (IY+d)

Source→ Dest Bit↓	(IY+d)
0	$FDC8d86
1	$FDC8d8E
2	$FDC8d96
3	$FDC8d9E
4	$FDC8dA6
5	$FDC8dAE
6	$FDC8dB6
7	$FDC8dBE

(IY+d)b

b

(IY+d)b ← 1

b, (IY+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

Resets bit b of the byte stored at the memory address generated by adding the contents of the IY register to the two's complement displacement d. (Sets it as 0).
No flags are affected.

RET - RETurn from subroutine

Pops previous program counter (PC) from stack before calling a subroutine and continues executing, effectively returning execution to the point in the program before calling the subroutine. No flags are affected.

The following table shows the conditions possible and their relevant flags.

Condition	Flag
Sign-Positive (P)	S
Sign-Negative (N)	S
Non-Zero (NZ)	Z
Zero (Z)	Z
Parity-Odd (PO)	P/V
Parity-Even (PE)	P/V
No-Carry (NC)	C
Carry (C)	C

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

RET

Source→ Dest↓	(sp, sp+1)
PC	$C9

PC

pCL ← (sp)
pCH ← (sp+1)

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 10 / 2.50

Pop previous PC from calling the routine from stack and resume execution from there

Conditional Direct

RET cc

Source→ Dest↓	NZ, (sp, sp+1)	Z, (sp, sp+1)	NC, (sp, sp+1)	C, (sp, sp+1)	PO, (sp, sp+1)	PE, (sp, sp+1)	P, (sp, sp+1)	M, (sp, sp+1)
PC	$C0	$C8	$D0	$D8	$E0	$E8	$F0	$F8

PC

cc

IF cc true {
pCL ← (sp)
pCH ← (sp+1) }

cc

S	Z	H	P/V	N	C
-	-	-	-	-	-

IF cc == true
3 / 11 / 2.75
IF cc == false
1 / 5 / 1.25

If cc (according to table above) is True, Pop previous PC from calling the routine from stack and resume execution from there. No flags are affected.

RETI - RETurn from Interrupt

Returns from a interrupt routine (identically to the ret instruction) but also signals an I/O device that the interrupt routine is completed. Nested interrupts are supported through the RETI instruction. Before returning, interrupts should be enabled to enable handling of interrupts that were not handled during the current interrupt routine. No flags are affected.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

RETI

Source→ Dest↓	(sp, sp+1)
PC	$ED4D

PC

(sp)

pCL ← (sp)
pCH ← (sp+1)

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

Pop previous PC from calling the routine from stack and resume execution from there, signal an I/O device that the interrupt routine has completed.

RETN - RETurn from Non-maskable interrupt

Returns from a non-maskable interrupt service routine (identically to the ret instruction). The state of IFF2 is copied back to IFF1 so that maskable interrupts are enabled immediately following the RETN if they were enabled before the nonmaskable interrupt. No flags are affected.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

RETN

Source→ Dest↓	(sp, sp+1)
PC	$ED45

PC

(sp)

pCL ← (sp)
pCH ← (sp+1)

None

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 14 / 3.50

Pop previous PC from calling the routine from stack and resume execution from there, copy state of IFF2 back to IFF1 to renable maskable interrupts if they were enabled before the routine was entered.

RL - Rotate Left

Rotate register left by 1 position. The sign-bit (Bit 7) is copied to the carry flag. The previous content of the carry flag are copied to bit 0. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

RL r

Source→ Dest↓	A	B	C	D	E	H	L
RL	$CB17	$CB10	$CB11	$CB12	$CB13	$CB14	$CB15

r = (a,b,c,d,e,h,l)

RL

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Rotates the register, a, b, c, d, e, h or l left by 1 position. The sign-bit (bit-7) is copied to the carry flag as well. The previous carry flag becomes bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Register-Indirect

RL (HL)

Source→ Dest↓	(HL)
RL	$CB16

(HL)

RL

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Rotates the byte in memory pointed at by the register pair HL left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag. The previous carry flag becomes bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

RL (IX+d)

Source→ Dest↓	(IX+d)
RL	$DDCBd16

(IX+d)

RL

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag, the previous carry flag becomes bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

RL (IY+d)

Source→ Dest↓	(IY+d)
RL	$FDCBd16

(IY+d)

RL

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag, the previous carry flag becomes bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

RLA - Rotate Left Accumulator

Rotate the accumulator left by 1 position through the carry flag. The carry flag becomes bit 0. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied

RLA

Source→ Dest↓	A
RLA	$17

A

RL

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Rotates accumulator left one position through the carry flag, making the carry bit bit 0.
S, Z and P/V are not affected.
H and N are reset.
Carry bit is bit 7 from Accumulator before the operation

RLC - Rotate Left Circular

Rotate register left by 1 position. The sign-bit (Bit 7) is copied to both bit 0, and the carry flag. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

RLC r

Source→ Dest↓	A	B	C	D	E	H	L
RLC	$CB07	$CB00	$CB01	$CB02	$CB03	$CB04	$CB06

r = (a,b,c,d,e,h,l)

RL

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Rotates the register, a, b, c, d, e, h or l left by 1 position. The sign-bit (bit-7) is copied to the carry flag as well as to bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Register-Indirect

RLC (HL)

Source→ Dest↓	(HL)
RLC	$CB0E

(HL)

RL

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Rotates the byte in memory pointed at by the register pair HL left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag as well as to bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

RLC (IX+d)

Source→ Dest↓	(IX+d)
RLC	$DDCBd06

(IX+d)

RL

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag as well as to bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

RLC (IY+d)

Source→ Dest↓	(IY+d)
RLC	$FDCBd06

(IY+d)

RL

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag as well as to bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

RLCA - Rotate Left Circular Accumulator

Rotate the accumulator left by 1 position. The sign-bit (Bit 7) is copied to both bit 0 as well as the carry flag. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied

RLCA

Source→ Dest↓	A
RLCA	$07

A

RL

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Rotates accumulator left one position, also copies sign-bit to carry bit.
S, Z and P/V are not affected.
H and N are reset.
Carry bit is bit 7 from Accumulator before the operation

RLD - Rotate Left Decimal

The lower nibble of the memory location pointed to by the HL register pair are copied to the high-nibble of the same memory location. The previous contents of the higher-order bits of the memory location pointed to by the HL register pair are moved to the lower nibble of the Accumulator. The higher nibble of the Accumulator remains untouched.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied

RLD

Source→ Dest↓	(HL)
RLD	$ED6F

(HL), A

A, 0,3 ← (HL, 4-7)
(HL, 4-7) ← (HL, 0-3)

None

S	Z	H	P/V	N	C
-	✓	✓	✓	✓	-

5 / 18 / 4.50

This function is used in BCD operations. Copies the lower nibble of the memory location pointed to by HL to the higher location, and moves that location over to the lower bits of the Accumulator.
Z is set if the accumulator is 0 after an operation, otherwise reset.
P/V is set if parity of the Accumulator is even after the operation, reset otherwise
H and N are reset and C is not affected.

RR - Rotate Right

Rotate register right by 1 position through the carry flag. Bit 0 is copied to the carry flag and the previous contents of the carry flag is copied to bit 7. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

RR r

Source→ Dest↓	A	B	C	D	E	H	L
RR	$CB1F	$CB18	$CB19	$CB1A	$CB1B	$CB1C	$CB1D

r = (a,b,c,d,e,h,l)

RR

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Rotates the register, a, b, c, d, e, h or l right by 1 position. The contents of bit 0 are copied to the carry flag. The previous carry flag becomes bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Register-Indirect

RR (HL)

Source→ Dest↓	(HL)
RR	$CB1E

(HL)

RR

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Rotates the byte in memory pointed at by the register pair HL right by 1 bit. The contents of bit 0 are copied to the carry flag. The previous carry flag becomes bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

RR (IX+d)

Source→ Dest↓	(IX+d)
RR	$DDCBd1E

(IX+d)

RR

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag. The previous carry flag becomes bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

RR (IY+d)

Source→ Dest↓	(IY+d)
RR	$FDCBd1E

(IY+d)

RR

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag. The previous carry flag becomes bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

RRA - Rotate Right Accumulator

Rotate the accumulator right by 1 position through the carry flag. The carry flag becomes bit 7. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Direct

RRA

Source→ Dest↓	A
RRA	$1F

A

RR

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Rotates accumulator right one position through the carry flag, making the carry bit bit 7.
S, Z and P/V are not affected.
H and N are reset.
Carry bit is bit 0 from Accumulator before the operation

RRC - Rotate Right Circular

Rotate register right by 1 position. Bit 0 is copied to both bit 7, and the carry flag. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

RRC r

Source→ Dest↓	A	B	C	D	E	H	L
RRC	$CB0F	$CB08	$CB09	$CB0A	$CB0B	$DB0C	$CB0D

r = (a,b,c,d,e,h,l)

RR

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Rotates the register, a, b, c, d, e, h or l left by 1 position. The sign-bit (bit-7) is copied to the carry flag as well as to bit 0.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Register-Indirect

RRC (HL)

Source→ Dest↓	(HL)
RRC	$CB0E

(HL)

RR

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Rotates the byte in memory pointed at by the register pair HL right by 1 bit. The contents of bit 0 are copied to the carry flag as well as to bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

RRC (IX+d)

Source→ Dest↓	(IX+d)
RRC	$DDCBd0E

(IX+d)

RR

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag as well as to bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

RRC (IY+d)

Source→ Dest↓	(IY+d)
RRC	$FDCBd0E

(IY+d)

RR

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d right by 1 bit. The contents of bit 0 copied to the carry flag as well as to bit 7.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

RRCA - Rotate Right Circular Accumulator

Rotate the accumulator right by 1 position. Bit 0 is copied to the carry flag, as well as to bit 7. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Direct

RRCA

Source→ Dest↓	A
RRCA	$0F

A

RR

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Rotates accumulator right one position, also copies bit 0 to carry bit as well as to bit 7.
S, Z and P/V are not affected.
H and N are reset.
Carry bit is bit 0 from Accumulator before the operation

RRD - Rotate Right Decimal

The lower nibble of the memory location pointed to by the HL register pair are copied to the lower-nibble of the Accumulator. The previous contents of the lower nibble of the Accumulator are copied to the higher nibble of the memory location pointed to by the register pair HL and the higher nibble of memory location pointed to by the HL register pair is copied to the lower nibble of the same location. The higher nibble of the Accumulator remains untouched.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Implied

RRD

Source→ Dest↓	(HL)
RDD	$ED67

(HL), A

A, 0,3 ← (HL, 0-3)
(HL, 0-3) ← (HL, 4-7)

None

S	Z	H	P/V	N	C
-	✓	✓	✓	✓	-

5 / 18 / 4.50

This function is used in BCD operations. Copies the higher nibble of the memory location pointed to by HL to the lower location, and moves that location over to the lower bits of the Accumulator.
S is set if the Accumulator is negative after an operation, otherwise reset
Z is set if the accumulator is 0 after an operation, otherwise reset.
P/V is set if parity of the Accumulator is even after the operation, reset otherwise
H and N are reset and C is not affected.

RST - ReSeT

Pushes High byte of current program counter to SP-1, and low byte of current program counter to SP-2. Then it loads the high byte of PC with 0, and uses the value of p to load the low byte. The processor then resumes executing from zero page. No flags are affected.

The following table shows the possible value of p and the zero page address where execution resumes.

p	PC address
$00	0000
$08	$0008
$10	$0010
$18	$0018
$20	$0020
$28	$0028
$30	$0030
$38	$0038

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-Indirect

RST p

Source→ Dest↓	p=0	p=8	p=16	p=24	p=32	p=40	p=48	p=56
PC=$00+p	$C7	$CF	$D7	$DF	$E7	$EF	$F7	$FF

PC

p

(SP – 1) ← PCH
(SP – 2) ← PCL
PC ← $00p

p

S	Z	H	P/V	N	C
-	-	-	-	-	-

3 / 11 / 2.75

Reset and resume execution from zero page address indicated by p (see table above).

SBC - SuBtract with Carry

Subtract register or memory contents, with or without an offset, with carry, from the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Register

SBC A, r

Source→ Dest↓	A	B	C	D	E	H	L
SBC	$9F	$98	$99	$9A	$9B	$9C	$9D

A

r = (a, b, c, d, e, h, l)

A ← A - r - CY

A, r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

Contents of register r are subtracted from the Accumulator with carry and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Immediate-to-Register

SBC A, n

Source→ Dest↓	n
SBC	$DE

A

n

A ← A - n - CY

A, n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Contents of integer n are subtracted from the Accumulator with carry and the result is stored in the Accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Register-Indirect-to-Register

SBC A, (HL)

Source→ Dest↓	(HL)
SBC	$9E

A

(HL)

A ← A - (HL) - CY

A, (HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

The byte at the address pointed to by the HL register pair and the carry is subtracted from the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Indexed-to-Register

SBC A, (IX+d)

Source→ Dest↓	(IX+d)
SBC	$DD9Ed

A

(IX+d)

A ← A - (IX+d) - CY

A, (IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IX register to the two's complement displacement d, is subtracted from the accumulator along with carry and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Indexed-to-Register

SBC A, (IY+d)

Source→ Dest↓	(IY+d)
SBC	$FD9Ed

A

(IY+d)

A ← A - (IY+d) - CY

A, (IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IY register to the two's complement displacement d, is subtracted from the accumulator along with carry and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

16-bit operations

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register to Register

SBC HL, ss

Source→ Dest↓	BC	DE	HL	SP
SBC HL	$ED42	$ED52	$ED62	$ED72

HL

ss =( bc, de, hl, sp)

HL ← HL - ss - CY

HL, ss

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

4 / 15 / 3.75

The contents of register pairs bc, de, hl or sp are subtracted from the contents of register pair hl along with carry flag (C flag in F register) and the result is stored in HL
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 12, otherwise it is reset.
P/V is set if overflow, otherwise it is reset.
N is set, C is set if borrow, otherwise reset

SCF - Set Carry Flag

The carry flag in the F register is set.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Bit

SCF

Source→ Dest↓	CY
CY=1	$37

CY

CY ← 1

None

S	Z	H	P/V	N	C
-	-	✓	-	✓	✓

1 / 4 / 1.0

Sets the carry flag in the F register.
The H bit is reset.
N is reset, C is set to 1

SET - SET bit

Set a bit in register or memory, with or without offset.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

SET b, r

Source→ Dest Bit↓	A	B	C	D	E	H	L
0	$C8C7	$C8C0	$C8C1	$C8C2	$C8C3	$C8C4	$C8C5
1	$C8CF	$C8C8	$C8C9	$C8CA	$C8CB	$C8CC	$C8CD
2	$C8D7	$C8D0	$C8D1	$C8D2	$C8D3	$C8D4	$C8D5
3	$C8DF	$C8D8	$C8D9	$C8DA	$C8DB	$C8DC	$C8DD
4	$C8E7	$C8E0	$C8E1	$C8E2	$C8E3	$C8E4	$C8E5
5	$C8EF	$C8E8	$C8E9	$C8EA	$C8EB	$C8EC	$C8ED
6	$C8F7	$C8F0	$C8F1	$C8F2	$C8F3	$C8F4	$C8F5
7	$C8FF	$C8F8	$C8F9	$C8FA	$C8FB	$C8FC	$C8FD

r=(a,bc,d,e,h,l)b

b

rb ← 1

b, r

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 8 / 2.00

Set bit b of register r to 1.
No flags are affected

Register-Indirect

SET b, (HL)

Source→ Dest Bit↓	(HL)
0	$C8C6
1	$C8CE
2	$C8D6
3	$C8DE
4	$C8E6
5	$C8EE
6	$C8F6
7	$C8FE

(HL)b

b

(HL)b ← 1

b, (HL)

S	Z	H	P/V	N	C
-	-	-	-	-	-

4 / 15 / 3.75

Set bit b of the byte pointed to by memory location stored in register pair HL as 1.
No falgs are affected.

Indexed

SET b, (IX+d)

Source→ Dest Bit↓	(IX+d)
0	$DDC8dC6
1	$DDC8dCE
2	$DDC8dD6
3	$DDC8dDE
4	$DDC8dE6
5	$DDC8dEE
6	$DDC8dF6
7	$DDC8dFE

(IX+d)b

b

(IX+d)b ← 1

b, (IX+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

Set bit b of the byte stored at the memory address generated by adding the contents of the IX register to the two's complement displacement d to 1
No flags are affected

Indexed

SET b, (IY+d)

Source→ Dest Bit↓	(IY+d)
0	$FDC8dC6
1	$FDC8dCE
2	$FDC8dD6
3	$FDC8dDE
4	$FDC8dE6
5	$FDC8dEE
6	$FDC8dF6
7	$FDC8dFE

(IY+d)b

b

(IY+d)b ← 1

b, (IY+d)

S	Z	H	P/V	N	C
-	-	-	-	-	-

6 / 23 / 5.75

Set bit b of the byte stored at the memory address generated by adding the contents of the IY register to the two's complement displacement d as 1.
No flags are affected.

SLA - Shift Left Arithmetic

Shift register left by 1 position. Bit 0 is reset. The sign-bit (Bit 7) is copied to the carry flag. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

SLA r

Source→ Dest↓	A	B	C	D	E	H	L
SLA	$CB27	$CB20	$CB21	$CB22	$CB23	$CB24	$CB25

r = (a,b,c,d,e,h,l)

SL

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Shifts the register, a, b, c, d, e, h or l left by 1 position. The sign-bit (bit-7) is copied to the carry flag.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Register-Indirect

SLA (HL)

Source→ Dest↓	(HL)
SLA	$CB26

(HL)

SL

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Shifts the byte in memory pointed at by the register pair HL left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

SLA (IX+d)

Source→ Dest↓	(IX+d)
SLA	$DDCBd26

(IX+d)

SL

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

SLA (IY+d)

Source→ Dest↓	(IY+d)
SLA	$FDCBd26

(IY+d)

SL

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

SLL - Shift Logical Left

This is an undocumented opcode, while it does work on a real z80, it might not work on derivatives or on some emulators.
It is identical to the SLA instruction, except for setting bit 0 to 1 (where as SLA sets it to 0).
The indexed variation of these instructions are particularly dubious and there is conflicting documentation on whether they exist or work as expected

Shift register logcally left by 1 position. Bit 0 is set to 1. The sign-bit (Bit 7) is copied to the carry flag. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

SLA r

Source→ Dest↓	A	B	C	D	E	H	L
SLL	$CB37	$CB30	$CB31	$CB32	$CB33	$CB34	$CB35

r = (a,b,c,d,e,h,l)

SL

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Shifts the register, a, b, c, d, e, h or l left by 1 position. The sign-bit (bit-7) is copied to the carry flag. Bit 0 is set to 1.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Register-Indirect

SLL (HL)

Source→ Dest↓	(HL)
SLA	$CB36

(HL)

SL

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Shifts the byte in memory pointed at by the register pair HL left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag. Bit 0 is set to 1.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

SLL (IX+d)

Source→ Dest↓	(IX+d)
SLA	$DDCBd36

(IX+d)

SL

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag. Bit 0 is set to 1.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

Indexed

SLL (IY+d)

Source→ Dest↓	(IY+d)
SLA	$FDCBd36

(IY+d)

SL

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d left by 1 bit. The contents of the sign-bit (bit 7) are copied to the carry flag. Bit 0 is set to 1.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 7 of the register before the operation

SRA - Shift Right Arithmetic

Shift register right by 1 position. The contents of bit 0 are copied to the carry flag and the previous contents of the sign-bit, bit 7 remains unchanged. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

SRA r

Source→ Dest↓	A	B	C	D	E	H	L
SRA	$CB2F	$CB28	$CB29	$CB2A	$CB2B	$CB2C	$CB2D

r = (a,b,c,d,e,h,l)

SR

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Shiftse register, a, b, c, d, e, h or l right by 1 position. The contents of bit 0 are copied to the carry flag, but bit-7 remains unchanged.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Register-Indirect

SRA (HL)

Source→ Dest↓	(HL)
SRA	$CB2E

(HL)

SR

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Shifts the byte in memory pointed at by the register pair HL right by 1 bit. The contents of bit 0 are copied to the carry flag, but bit-7 remains unchanged.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

SRA (IX+d)

Source→ Dest↓	(IX+d)
SRA	$DDCBd3E

(IX+d)

SR

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag, but bit-7 remains unchanged.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

Indexed

SRA (IY+d)

Source→ Dest↓	(IY+d)
SRA	$FDCBd3E

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Rotates the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag, but bit-7 remains unchanged.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H and N are reset
P/V is set if parity is even, otherwise reset.
Carry is copied from bit 0 of the register before the operation

SRL - Shift Right Logical

Rotate register right by 1 position. The contents of bit 0 are copied to the carry flag and bit 7 is reset. Bit 0 is the least significant bit.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register

SRL r

Source→ Dest↓	A	B	C	D	E	H	L
SRL	$CB3F	$CB38	$CB39	$CB3A	$CB3B	$CB3C	$CB3D

r = (a,b,c,d,e,h,l)

SR

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 8 / 2.0

Shifts the register, a, b, c, d, e, h or l right by 1 position. The contents of bit 0 are copied to the carry flag, and bit-7 is reset.
S, H and N are reset
Z is set if result is 0, reset otherwise.
P/V is set if parity is even, otherwise reset
C is the data from bit 0 of the register

Register-Indirect

SRL (HL)

Source→ Dest↓	(HL)
SRL	$CB3E

(HL)

SR

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

4 / 15 / 3.75

Shifts the byte in memory pointed at by the register pair HL right by 1 bit. The contents of bit 0 are copied to the carry flag, and bit-7 is reset.
S, H and N are reset
Z is set if result is 0, reset otherwise.
P/V is set if parity is even, otherwise reset
C is the data from bit 0 of the register

Indexed

SRL (IX+d)

Source→ Dest↓	(IX+d)
SRL	$DDCBd3E

(IX+d)

SR

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IX register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag, and bit-7 is reset.
S, H and N are reset
Z is set if result is 0, reset otherwise.
P/V is set if parity is even, otherwise reset
C is the data from bit 0 of the register

Indexed

SRL (IY+d)

Source→ Dest↓	(IY+d)
SRL	$FDCBd3E

(IY+d)

SR

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

6 / 23 / 3.75

Shifts the byte at the memory address generated by adding the contents of the IY register to the two's complement displacement d right by 1 bit. The contents of bit 0 are copied to the carry flag, and bit-7 is reset.
S, H and N are reset
Z is set if result is 0, reset otherwise.
P/V is set if parity is even, otherwise reset
C is the data from bit 0 of the register

SUB - SUBtract

Subtract register or memory contents, with or without an offset, from the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

SUB r

Source→ Dest↓	A	B	C	D	E	H	L
SUB	$97	$90	$91	$92	$93	$94	$95

A

a, b, c, d, e, h, l

A ← A - r

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

Contents of register r are subtracted from the Accumulator and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Immediate-to-Implied

SUB n

Source→ Dest↓	n
SUB	$D6n

A

n

A ← A - n

n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

Contents of integer n are subtracted from the Accumulator and the result is stored in the Accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Register-Indirect-to-Implied

SUB (HL)

Source→ Dest↓	(HL)
SUB	$96

A

(HL)

A ← A - (HL)

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

The byte at the address pointed to by the HL register pair is subtracted from the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Indexed-to-Implied

SUB (IX+d)

Source→ Dest↓	(IX+d)
SUB	$DD96d

A

(IX+d)

A ← A - (IX+d)

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IX register to the two's complement displacement d, is subtracted from the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

Indexed-to-Implied

SUB (IY+d)

Source→ Dest↓	(IY+d)
SUB	$FD96d

A

(IY+d)

A ← A - (IY+d)

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

The byte at the address generated by adding the contents of the IY register to the two's complement displacement d, is subtracted from the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is set if borrow from bit 4, otherwise reset.
P/V is set if overflow, otherwise is reset.
N is set. C is set if borrow, otherwise is reset.

XOR - Perform logical eXclusive OR with accumulator

Perform a logical exclusive OR operation between a register, integer or memory address, with or without offset, to the accumulator and store the result in the accumulator.

Mode

Instruction

Opcode

Destination

Source

Operation

Operands

Flags (Register F)

MC/TS/ET

Description

Register-to-Implied

XOR r

Source→ Dest↓	A	B	C	D	E	H	L
XOR	$AF	$A8	$A9	$AA	$AB	$AC	$AD

A

a, b, c, d, e, h, l

A ← A ⊕ r

r

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

1 / 4 / 1.0

A logical XOR operation is performed between the contents of r and the accumulator and the result is stored in the Accumulator. Register can be a, b, c, d, e, h or l.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Immediate-to-Implied

XOR n

Source→ Dest↓	n
XOR	$EEn

A

n

A ← A ⊕ n

n

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical XOR operation is performed between the integer n and the contents of the Accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Register-Indirect-to-Implied

XOR (HL)

Source→ Dest↓	(HL)
XOR	$AE

A

(HL)

A ← A ⊕ (HL)

(HL)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

2 / 7 / 1.75

A logical XOR operation is performed between the byte at the address pointed to by the HL register pair and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

XOR (IX+d)

Source→ Dest↓	(IX+d)
XOR	$DDAEd

A

(IX+d)

A ← A ⊕ (IX+d)

(IX+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical XOR operation is performed between the byte at the address generated by adding the contents of the IX register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Indexed-to-Implied

XOR (IY+d)

Source→ Dest↓	(IY+d)
XOR	$FDAEd

A

(IY+d)

A ← A ⊕ (IY+d)

(IY+d)

S	Z	H	P/V	N	C
✓	✓	✓	✓	✓	✓

5 / 19 / 4.75

A logical XOR operation is performed between the byte at the address generated by adding the contents of the IY register to the two's complement displacement d, and the accumulator and the result is stored in the accumulator to the accumulator and the result stored in the accumulator.
S is set if result is negative, otherwise reset.
S is set if result is negative, otherwise reset.
Z is set if result is 0, otherwise reset.
H is reset.
P/V is set if overflow, otherwise is reset.
N is reset. C is reset

Opcode	Instruction
$DDCB10C0	SET 0, (IX+10), B
$DDCB10C1	SET 0, (IX+10), C
$DDCB10C2	SET 0, (IX+10), D
$DDCB10C3	SET 0, (IX+10), E
$DDCB10C4	SET 0, (IX+10), H
$DDCB10C5	SET 0, (IX+10), L
$DDCB10C6	SET 0, (IX+10) - Documented
$DDCB10C7	SET 0, (IX+10), A

Opcode	Instruction	Opcode	Instruction	Opcode	Instruction	Opcode	Instruction
$ED40	IN B, (C)	$ED50	IN D, (C)	$ED60	IN H, (C)	$ED70	IN (C) / IN F, C()**
$ED41	OUT (C), B	$ED51	OUT (C), D	$ED61	OUT (C), H	$ED71	OUT (C), 0**
$ED42	SBC HL, BC	$ED52	SBC HL, DE	$ED62	SBC HL, HL	$ED72	SBC HL, SP
$ED43	LD (nn), BC	$ED53	LD (nn), DE	$ED63	LD (nn), HL	$ED73	LD (nn), SP
$ED44	NEG	$ED54	NEG**	$ED64	NEG**	$ED74	NEG**
$ED45	RETN	$ED55	RETN**	$ED65	RETN**	$ED75	RETN**
$ED46	IM 0	$ED56	IM 1	$ED66	IM 0**	$ED76	IM 1**
$ED47	LD I, A	$ED57	LD A, I	$ED67	RRD	$ED77	NOP**
$ED48	IN C, (C)	$ED58	IN E, (C)	$ED68	IN L, (C)	$ED78	IN A, (C)
$ED49	OUT (C), C	$ED59	OUT (C), E	$ED69	OUT (C), L	$ED79	OUT (C), A
$ED4A	ADC HL, BC	$ED5A	ADC HL, DE	$ED6A	ADC HL, HL	$ED7A	ADC HL, SP
$ED4B	LD BC, (nn)	$ED5B	LD DE, (nn)	$ED6B	LD HL, (nn)	$ED7B	LD SP, (nn)
$ED4C	NEG**	$ED5C	NEG**	$ED6C	NEG**	$ED7C	NEG**
$ED4D	RETI	$ED5D	RETN**	$ED6D	RETN**	$ED7D	RETN**
$ED4E	IM 0**	$ED5E	IM 2	$ED6E	IM 0**	$ED7E	IM 2**
$ED4F	LD R, A	$ED5F	LD A, R	$ED6F	RLD	$ED7F	NOP**

z80 Instruction list, Timing, Flags, Addressing

Registers

1) This is not strictly true, when you place the accumulator on the I/O bus, the B register is placed with it, indicating that they can be used as a pair. It is also paired with the F register.

Flags in detail

Notations used

Instructions

Undocumented opcodes

**These are completely undocumented

References

load	trans	stack	shift	logic	arith	incl	ctrl	brnch	flags	repeat	wait	undoc

IN	EX	POP	RL	AND	ADC	DEC	CALL	DJNZ	CCF	CPDR	HALT	SLL
IND	EXX	PUSH	RLA	BIT	ADD	INC	RET	JP	DI	CPIR	NOP	DD prefix
INI			RLC	CPL	CP		RETI	JR	EI	INDR		ED prefix
LD			RLCA	OR	CPD		RETN		IM	INIR		FD prefix
LDD			RLD	RES	CPI		RST		SCF	LDDR		DDCB pr
LDI			RR	SET	DAA					LDIR
OUT			RRA	XOR	NEG					OTDR
OUTD			RRC		SBC					OTIR
OUTI			RRCA		SUB
			RRD
			SLA
			SRA
			SRL

	PC	SP	IX	IY	I	R	A	F	B	C	D	E	H	L	A'	F'	B'	C'	D'	E'	H'	L'
Width	16-bit	16-bit	16-bit	16-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit	8-bit
Type	Program Counter	Stack Pointer	Index Register	Index Register	Interrupt Vector	Memory Refresh	Acummul.	Flags	General Purpose	General Purpose	General Purpose	General Purpose	General Purpose	General Purpose	Accumul.	Flags	General Purpose	General Purpose	General Purpose	General Purpose	General Purpose	General Purpose
Used for	Opcode Execution Pointer	Top of stack Pointer	Memory offset register	Memory offset register	Interrupt address	DRAM refresh	Arithmetic	Condition Flags	Byte Counter	I/O device selector	Any	Any	Memory pointer (with L)	Memory pointer (with H)	Arithmetic	Condition Flags	Byte Counter	I/O device select	Any	Any	Memory pointer (With L')	Memory pointer (With H')
16-bit pair	Itself	Itself	Itself	Itself	None	None	None¹	None¹	BC	BC	DE	DE	HL	HL	None¹	None¹	BC'	BC'	DE'	DE'	HL'	HL'
Shadow	None	None	None	None	None	None	A'	F'	B'	C'	D'	E'	H'	L'	A	F	B	C	D	E	H	L

Operation	Carry	Half Carry	Upper Nibble	Lower Nibble	Number added	Carry after
	0	0	9-0	0-9	00	0
	0	0	0-8	A-F	06	0
	0	1	0-9	0-3	06	0
	1	0	0-2	0-9	60	1
	1	0	0-2	A-F	66	1
	1	1	0-3	0-3	66	1
ADD	0	0	A-F	0-9	60	1
ADC	0	0	9-F	A-F	66	1
INC	0	1	A-F	0-3	66	1
SUB	0	0	0-9	0-9	00	0
SBC	0	1	0-8	6-F	FA	0
DEC	1	0	7-F	0-9	A0	1
NEG	1	1	6-7	6-F	9A	1

Operation	Carry	Half Carry	Upper Nibble	Lower Nibble	Number added	Carry after
	0	0	9-0	0-9	00	0
	0	0	0-8	A-F	06	0
	0	1	0-9	0-3	06	0
	1	0	0-2	0-9	60	1
	1	0	0-2	A-F	66	1
	1	1	0-3	0-3	66	1
ADD	0	0	A-F	0-9	60	1
ADC	0	0	9-F	A-F	66	1
INC	0	1	A-F	0-3	66	1
SUB	0	0	0-9	0-9	00	0
SBC	0	1	0-8	6-F	FA	0
DEC	1	0	7-F	0-9	A0	1
NEG	1	1	6-7	6-F	9A	1

Operation	Carry	Half Carry	Upper Nibble	Lower Nibble	Number added	Carry after
	0	0	9-0	0-9	00	0
	0	0	0-8	A-F	06	0
	0	1	0-9	0-3	06	0
	1	0	0-2	0-9	60	1
	1	0	0-2	A-F	66	1
	1	1	0-3	0-3	66	1
ADD	0	0	A-F	0-9	60	1
ADC	0	0	9-F	A-F	66	1
INC	0	1	A-F	0-3	66	1
SUB	0	0	0-9	0-9	00	0
SBC	0	1	0-8	6-F	FA	0
DEC	1	0	7-F	0-9	A0	1
NEG	1	1	6-7	6-F	9A	1